71. Grams. S. Lin and you may J. B. Kuo, “Fringing-Created Narrow-Channel-Effect (FINCE) Related Capacitance Choices of Nanometer FD SOI NMOS Devices Using Mesa-Isolation Thru three-dimensional Simulation” , EDSM , Taiwan ,
72. J. B. Kuo, “Progression regarding Bootstrap Techniques in Low-Current CMOS Electronic VLSI Circuits for SOC Software” , IWSOC , Banff, Canada ,
P. Yang, “Entrance Misalignment Impression how much is chat on rosebrides? Associated Capacitance Decisions regarding an effective 100nm DG FD SOI NMOS Equipment having n+/p+ Poly Most readily useful/Base Entrance” , ICSICT , Beijing, China
73. Grams. Y. Liu, N. C. Wang and you may J. B. Kuo, “Energy-Effective CMOS Higher-Stream Rider Routine with the Subservient Adiabatic/Bootstrap (CAB) Way of Reduced-Energy TFT-Lcd Program Apps” , ISCAS , Kobe, Japan ,
74. Y. S. Lin, C. H. Lin, J. B. Kuo and you can K. W. Su, “CGS Capacitance Technology from 100nm FD SOI CMOS Products that have HfO2 High-k Door Dielectric Provided Vertical and you will Fringing Displacement Effects” , HKEDSSC , Hong kong ,
75. J. B. KUo, C. H. Hsu and you will C. P. Yang, “Gate-Misalignment Related Capacitance Choices out of a 100nm DG SOI MOS Gizmos that have Letter+/p+ Top/Base Entrance” , HKEDSSC , Hong kong ,
76. G. Y. Liu, Letter. C. Wang and you can J. B. Kuo, “Energy-Productive CMOS Higher-Load Rider Routine into the Complementary Adiabatic/Bootstrap (CAB) Way of Reduced-Fuel TFT-Lcd System Programs” , ISCAS , Kobe, Japan ,
77. H. P. Chen and you will J. B. Kuo, “An excellent 0.8V CMOS TSPC Adiabatic DCVS Logic Circuit on the Bootstrap Technique to possess Lower-Electricity VLSI” , ICECS , Israel ,
B. Kuo, “A novel 0
80. J. B. Kuo and you can H. P. Chen, “A decreased-Voltage CMOS Weight Driver into the Adiabatic and Bootstrap Techniques for Low-Electricity Program Apps” , MWSCAS , Hiroshima, Japan ,
83. M. T. Lin, E. C. Sunshine, and you can J. B. Kuo, “Asymmetric Door Misalignment Effect on Subthreshold Attributes DG SOI NMOS Gizmos Considering Fringing Electronic Field-effect” , Electron Gizmos and you will Topic Symposium ,
84. J. B. Kuo, E. C. Sun, and Yards. T. Lin, “Studies off Door Misalignment Effect on the newest Tolerance Voltage out-of Twice-Gate (DG) Ultrathin FD SOI NMOS Gadgets Having fun with a tight Design Provided Fringing Digital Field effect” , IEEE Electron Gadgets to possess Microwave and you can Optoelectronic Software ,
86. Age. Shen and J. 8V BP-DTMOS Blogs Addressable Memory Cell Routine Produced by SOI-DTMOS Procedure” , IEEE Meeting toward Electron Products and you may Solid state Circuits , Hong kong ,
87. P. C. Chen and J. B. Kuo, “ic Reason Routine Having fun with a direct Bootstrap (DB) Technique for Low-voltage CMOS VLSI” , Around the world Symposium towards Circuits and you will Assistance ,
89. J. B. Kuo and you can S. C. Lin, “Lightweight Breakdown Model to own PD SOI NMOS Products Offered BJT/MOS Perception Ionization getting Liven Circuits Simulation” , IEDMS , Taipei ,
90. J. B. Kuo and you will S. C. Lin, “Compact LDD/FD SOI CMOS Product Design Given Opportunity Transport and you will Worry about Heat having Spice Circuit Simulation” , IEDMS , Taipei ,
91. S. C. Lin and you can J. B. Kuo, “Fringing-Triggered Burden Minimizing (FIBL) Negative effects of 100nm FD SOI NMOS Gadgets with a high Permittivity Door Dielectrics and LDD/Sidewall Oxide Spacer” , IEEE SOI Meeting Proc , Williamsburg ,
ninety five. J. B. Kuo and you can S. C. Lin, “The brand new Fringing Electronic Field-effect for the Quick-Station Perception Endurance Voltage out-of FD SOI NMOS Gadgets that have LDD/Sidewall Oxide Spacer Construction” , Hong kong Electron Products Meeting ,
93. C. L. Yang and J. B. Kuo, “High-Heat Quasi-Saturation Model of High-Current DMOS Strength Gizmos” , Hong-kong Electron Gadgets Conference ,
94. Elizabeth. Shen and you may J. B. Kuo, “0.8V CMOS Blogs-Addressable-Recollections (CAM) Phone Ciurcuit with a simple Mark-Compare Functionality Playing with Vast majority PMOS Active-Threshold (BP-DTMOS) Technique Predicated on Important CMOS Tech getting Reduced-Voltage VLSI Systems” , Around the world Symposium with the Circuits and Assistance (ISCAS) Legal proceeding , Washington ,